The embodiment relates to a method of processing a Wideband Code Division Multiple Access (WCDMA) signal timing offset for a signal analyzer, and more particularly, to a method of processing a WCDMA signal timing offset for a signal analyzer, which is capable of estimating and compensating for a timing offset at a high accuracy within 1% EVM (0.1 sample) by using Fast Fourier Transform (FFT) or Inverse Fourier Transform (IFFT) and a fractional RRC filter even while using a low sampling frequency of twice the WCDMA chip rate.
As well known in the art, WCDMA (Wideband Code Division Multiple Access) defined in 3GPP TS.25 standard, which is one of 3rd generation wireless communication systems, is an asynchronous mobile communication scheme having a chip rate of Fc=3.84 Mcps.
FIG. 1 is a view illustrating a radio frame structure of the WCDMA system including a synchronous channel. As shown in FIG. 1, according to the radio frame structure of the WCDMA system, chips are transmitted within a TTI (Transmission Time Interval) and each TTI includes one radio frame to 8 radio frames. Each radio frame is a duration of 10 ms and is divided into 15 slots. The slot includes 2560 chips. Thus, the TTI may include 15 to 120 slots.
Meanwhile, the primary synchronization channel includes a modulation code of 256 chips. The same modulation code is transmitted through primary synchronization channel at the same location in each slot. Since the secondary synchronization channel is a code sequence formed by combining modulation codes each having 256 chips, which correspond to 15 slots of one radio frame, the modulation codes of the secondary synchronization channel each is transmitted in parallel with the codes of the first synchronization channel every slot and are configured to be different from each other every slot.
The WCDMA system having the frame structure described above performs the cell search and physical layer synchronization to detect a downlink WCDMA signal through following three steps.
First step: The slot synchronization is obtained by synchronizing a sample/chip boundary through PSCH.
Second step: The frame synchronization and scrambling code are obtained through SSCH.
Third step: Fractional sample/chip boundary synchronization, scrambling code index synchronization and channel estimation through CPICH (Common Pilot Channel).
Until the CPICH is decoded, it is impossible to estimate the channel and exactly detect a remaining DPxCH signal such as s DPDCH (Dedicated Physical Data Channel) signal or a DPCCH (Dedicated Physical Control Channel) signal. The frequency, timing and phase offsets are estimated and compensated by using the detected CPICH signal so that the channel is estimated.
The WCDMA communication technique uses a symbol modulation scheme of a chip rate very higher than a data rate. In this case, since the sampling timing offset must be very smaller that the data sampling timing offset, the demodulation performance is very sensitive to the timing offset (error).
According to the related art, a maximum correlation value search scheme has been mainly used to estimate a timing offset. Thus, a signal analyzer according to the related art is required to perform an over sampling, which is 40 to 80 times the chip rate of 3.84 MHz of the WCDMA system, to maintain the condition of 1% EVM at the sampling frequency of 30.72 (=3.84*8) MHz, that is, the timing synchronization within 0.1 sample, so that too much resource is inefficiently consumed.